Test Generation of Crosstalk Delay Faults in VLSI Circuits

This book describes a variety of test generation algorithms for testing crosstalk delay faults in VLSI circuits. It introduces readers to the various crosstalk effects and describes both deterministic and simulation-based methods for testing crosstalk delay faults. The book begins with a focus on currently available crosstalk delay models, test generation algorithms for delay faults and crosstalk delay faults, before moving on to deterministic algorithms and simulation-based algorithms used to test crosstalk delay faults. Given its depth of coverage, the book will be of interest to design engineers and researchers in the field of VLSI Testing.\nTest Generation of Crosstalk Delay Faults in VLSI Circuits is written by S. Jayanthy; M.C. Bhuvaneswari and published by Springer. ISBNs for Test Generation of Crosstalk Delay Faults in VLSI Circuits are 9789811324932, 981132493X and the print ISBNs are 9789811324925, 9811324921.